NPTEL Advanced Computer Architecture Week 1 And 2 Assignment Answers 2025
1. In Dennard scaling, the___________ remains constant while the_________ increases exponentially.
- a) power-density, performance per watt ✅
- b) performance per watt, power-density
- c) performance per watt, number of transistors per chip
- d) number of transistors per chip, power-density
✅ Answer: a
Explanation: Dennard scaling states that as transistors get smaller, power density remains constant while performance increases, allowing more transistors to be used efficiently.
2. Select the most appropriate option.
S1: Two instructions can be executed simultaneously if there are no dependencies between them.
S2: ILP is the measure of the number of instructions that can be executed simultaneously.
- a) S1 true, S2 false
- b) S1 false, S2 true
- c) Both S1 and S2 are true ✅
- d) Both S1 and S2 are false
✅ Answer: c
Explanation: Both statements correctly describe ILP and parallel execution when no data/control dependencies exist.
3. Which of the following equations is correct regarding the cycles per instruction (CPI) metric?
- a) CPI = 1 + stall_rate * stall_penalty ✅
- b) CPI = 1 – stall_rate * stall_penalty
- c) CPI = 1 + stall_rate / stall_penalty
- d) CPI = 1 – stall_rate / stall_penalty
✅ Answer: a
Explanation: CPI increases with stalls. This formula reflects that ideal CPI (1) gets added to stalls caused by hazards.
4. In traditional pipelined processors, pipelining improves performance because it leads to ___pipeline stages which helps to _____ the clock frequency.
- a) smaller, decrease
- b) larger, decrease
- c) smaller, increase ✅
- d) larger, increase
✅ Answer: c
Explanation: Breaking execution into smaller pipeline stages reduces work per stage, allowing higher clock frequency.
5. Wrong path instructions are defined as the set of instructions after a branch in________ , which are executed if the branch is ___________
- a) data dependence order, taken
- b) data dependence order, not taken
- c) program order, not taken
- d) program order, taken ✅
✅ Answer: d
Explanation: Wrong-path instructions are from the taken path but were predicted incorrectly and speculatively executed in program order.
6. If a 5-stage pipeline with an issue width equal to n experiences no stalls, then the IPC is _______.
- a) n ✅
- b) n/2
- c) n/5
- d) n-1
✅ Answer: a
Explanation: With no stalls and issue width = n, we issue n instructions per cycle, hence IPC = n.
7. In out-of-order processors the execution is done in ____________ order where the instruction is always executed after the _________ instruction.
- a) program, consumer, producer
- b) data dependence, consumer, producer ✅
- c) data dependence, producer, consumer
- d) program, producer, consumer
✅ Answer: b
Explanation: Data dependency governs order. Execution waits until producer (data provider) executes before consumer.
8. Given a program with n instructions and n/5 branches. Assume that our processor can predict any given branch correctly with probability p, then probability of predicting all the branches correctly is _.
- a) (p)ⁿ⁄⁵ ✅
- b) (1 – p)ⁿ⁄⁵
- c) (p)ⁿ
- d) (1 – p)ⁿ
✅ Answer: a
Explanation: If there are n/5 branches and each is predicted with probability p, then overall probability = pⁿ⁄⁵
9. Which of the following is not a component of an instruction?
- a) Opcode
- b) Register IDs
- c) Constants
- d) Control signals ✅
✅ Answer: d
Explanation: Control signals are generated by the control unit during execution; they are not part of the instruction itself.
10. In a 5-stage pipeline, we stand to lose ________ successive cycle(s) after fetching a taken branch.
- a) 1
- b) 2 ✅
- c) 5
- d) 4
✅ Answer: b
Explanation: In a classic 5-stage pipeline (IF, ID, EX, MEM, WB), a taken branch typically causes 2 cycles of penalty due to misprediction or delay in branch resolution.
NPTEL Advanced Computer Architecture Week 2 Assignment Answers
1. Which dependencies are not respected by an out-of-order processor?
- a) Program order ✅
- b) Data
- c) Control
- d) None of the options
✅ Answer: a
Explanation: Out-of-order processors break program order for performance, but must respect data and control dependencies to maintain correctness.
2. In an out-of-order processor, register renaming is done in __________ order, and it converts the ________________registers to ____________ registers.
- a) out of, architectural, physical
- b) program, physical, architectural
- c) out of, physical, architectural
- d) program, architectural, physical ✅
✅ Answer: d
Explanation: Register renaming is done in program order to avoid false dependencies and maps architectural registers to physical registers.
3. What are the advantages of having a highly accurate branch predictor in an out-of-order processor? Choose the most appropriate option.
- a) Enable a large instruction window
- b) Maximize the ILP
- c) Increase IPC
- d) All of these ✅
✅ Answer: d
Explanation: Accurate prediction avoids pipeline flushes, enabling more ILP, higher IPC, and better instruction window utilization.
4. Select the most appropriate option for branch statements in an out-of-order processor.
S1: To predict the second branch, we do not need to predict the first branch.
S2: If we have branches in a bundle of 4 instructions, the instructions may not be contiguous.
- a) S1 true, S2 false
- b) S1 false, S2 true ✅
- c) Both true
- d) Both false
✅ Answer: b
Explanation: In S1, to predict the second branch, we must know the result of the first (due to control flow). S2 is true for VLIW/SIMD architectures.
5. Which of the following metrics of a processor does not get affected negatively by increasing the size of the instruction status table?
- a) Area
- b) Power consumption
- c) Latency
- d) Accuracy of branch predictor ✅
✅ Answer: d
Explanation: Branch predictor accuracy depends on prediction logic and history tracking, not instruction status table size.
6. Select the correct statement regarding a branch predictor?
- a) We do not use the branch predictor when we encounter unconditional branch and call/return instructions ✅
- b) Only call/return
- c) Only unconditional branch
- d) None
✅ Answer: a
Explanation: For unconditional branches and call/returns, the target is known, so prediction is unnecessary.
7. In a simple bimodal predictor, the current prediction is equal to the _____________.
- a) First branch outcome
- b) Most frequent outcome
- c) Last branch outcome ✅
- d) Least frequent outcome
✅ Answer: c
Explanation: Bimodal predictors (1-bit) use the last outcome to predict future behavior.
8. In a PAg predictor, which bits of the PC are used to index the table of GHRs (global history registers)?
- a) k LSB bits
- b) k MSB bits
- c) k continuous bits from somewhere in the middle ✅
- d) Random k bits
✅ Answer: c
Explanation: In PAg, specific middle bits (not just LSBs) of PC are chosen to index GHRs more uniformly and avoid aliasing.
9. In a Gap predictor that uses n bits of the program counter and k bits of the GHR, how many entries does the PHT have?
- a) 2ⁿ⁺ᵏ ✅
- b) 2ⁿ
- c) 2ᵏ
- d) 2ⁿ * k
✅ Answer: a
Explanation: GAp combines n PC bits + k GHR bits as a single index into the Pattern History Table (PHT), needing 2ⁿ⁺ᵏ entries.
10. For a very biased branch, we prefer to use a ____________. Try to find the most appropriate option that is the most accurate as well as the most hardware-efficient.
- a) Bimodal predictor with saturating counters ✅
- b) Pap predictor
- c) Pag predictor
- d) Bimodal without saturating counters
✅ Answer: a
Explanation: Saturating counters in a bimodal predictor provide stability against noisy branches — ideal for biased branches.