1. What is the main advantage of using a TLB?
- Increases program size
- Reduces memory fragmentation
- Speeds up address translation
- Simplifies memory management
Answer :- c
2. What is the minimum number of transistors required to build a functional SRAM cell?
- 2
- 4
- 6
- 8
Answer :- c
3. Choose the incorrect statement.
- MSHR is a hardware structure.
- MSHRs are essential for non-blocking caches.
- MSHR keeps record of all accesses to a missed cache block.
- MSHR has a single miss queue for all cache blocks
Answer :- d
4. Consider the following statements.
S1: Way prediction is an optimization technique for direct-mapped caches..
S2: Implementing replacement policies is simpler for skew-associative caches compared to set-associative caches..
.
- Only S1 is true.
- Only S2 is true.
- Both S1 and S2 are true.
- Both S1 and S2 are false.
Answer :- d
5. A VIPT cache requires an overlap of the ___________with the page offset.
- Page offset
- Set index
- Page index
- Tag field
Answer :- b
6. In a multi-banked cache, each MAT is composed of multiple________
- Banks
- Sub-banks
- Arrays
- Sub-arrays
Answer :- b
7. Loop tiling enhances the performance by ____________
- Reordering the loop iterations.
- Increasing the data locality within the loop body.
- Utilizing physical registers efficiently.
- Reducing loops in a program.
Answer :- b
8. Consider the following statements.
S1: Pipelined caches provide reduced access latency per memory access request compared to non-pipelined caches.
S2: Cacti is a tool used for modeling and simulating caches.
- Only S1 is true.
- Only S2 is true.
- Both S1 and S2 are true.
- Both S1 and S2 are false.
Answer :- b
9. In comparison to set-associative caches, what is the main advantage of a skew-associative cache?
- Simpler replacement policy
- Low area overhead
- Reduction in conflict misses
- Reduction in capacity misses
Answer :- c
10. Consider the following statements.
S1: Content-Addressable Memory (CAM) consumes more power than Static Random-Access Memory (SRAM) due to parallel searches.
S2: CAM is preferred over SRAM for implementing structures with a large number of entries.
- Only S1 is true.
- Only S2 is true.
- Both S1 and S2 are true.
- Both S1 and S2 are false.
Answer :- a
11. A trace is a sequence of _______ fetched from the ____.
- Basic blocks, i-cache
- Data blocks, d-cache
- Cache blocks, LLC
- DRAM rows, main memory
Answer :- a
12. Consider the following statements regarding a trace cache.
S1: The Fill buffer locally constructs the trace segment.
S2: Trace segments are stored in consecutive sets.
- Only S1 is true.
- Only S2 is true.
- Both S1 and S2 are true.
- Both S1 and S2 are false.
Answer :- c
13. Consider a case where i-cache misses have high repeatability and there is high correlation between consecutive misses (e.g., miss sequence A B … A B … A B … A B …). Which type of prefetcher leverages these types of patterns?
- Next line prefetcher
- Markov prefetcher
- Next block prefetcher
- Call graph prefetcher
Answer :- b
14. Which of the following prefetchers predict and prefetch the function that may be called next?
- Next line prefetcher
- Markov prefetcher
- Next block prefetcher
- Call graph prefetcher
Answer :- d
15. Consider the following statements.
S1: Shared memory is easier to program than message passing.
S2: Shared memory is less scalable compared to message passing.
- Only S1 is true.
- Only S2 is true.
- Both S1 and S2 are true.
- Both S1 and S2 are false.
Answer :- c
16. Which of the following highlights the fact that the potential speedup is limited by the portion of the computation that cannot be parallelized?
- Amdahl’s law
- Moore’s law
- Dennard scaling
- Murphy’s law
Answer :- a
17. Which category in the Flynn’s classification allows multiple processors to work independently on different tasks?
- SISD
- SIMD
- MISD
- MIMD
Answer :- d
18. ___________dynamically splits issue slots between threads (even in the same cycle).
- Hyperthreading
- SMT
- Coarse-grained multithreading
- Fine-grained multithreading
Answer :- b
19. Hyperthreading is SMT with _______________ partitioning.
- Static
- Dynamic
- Predictive
- Adaptive
Answer :- a
20. Which of the following suffers from the highest runtime thread scheduling overhead?
- SMT
- Hyperthreading
- Coarse-grained multithreading
- Fine-grained multithreading
Answer :- a
21. When a write operation is observed by all threads, it is referred to as ________.
- Write serialization
- Write propagation
- Write validation
- Write localization
Answer :- b
22. Consider the following statements.
S1: If a set of instructions is in SC, it will also be in PLSC.
S2: A set of instructions containing non-atomic writes cannot comply with PLSC.
- Only S1 is true.
- Only S2 is true.
- Both S1 and S2 are true.
- Both S1 and S2 are false.
Answer :- a
23. Which of the following statements is NOT correct ?
- The fence instruction is an example of a memory barrier.
- No instruction following the acquire instruction in program order can execute until it has been completed.
- The release instruction can only be completed if all the instructions before it have been fully completed.
- The store barrier is used to block both load and store operations.
Answer :- d
24. Consider the following statements.
S1: All instructions after the “fence” instruction cannot be executed until the “fence” instruction itself has been completed.
S2: The “fence” instruction cannot be executed until all preceding instructions have been completed.
- Only S1 is true.
- Only S2 is true.
- Both S1 and S2 are true.
- Both S1 and S2 are false.
Answer :- c
25. Which of the following are the key features of sequential consistency?
C1: Atomicity of writes
C2: Atomicity of reads
C3: Preservation of program order
- C3
- C2 and C3
- C1 and C3
- C1, C2 and C3
Answer :- c
26. Which of the following program order (po) edges are always global irrespective of the memory model?
- poRW , poRR
- poRR , poWR
- poWW , poWR
- poIS , poSI
Answer :- d
27. Which of the following are two kinds of rf (read-from) edges?
- rfe, rfi
- rfe, rfo
- rfi, rfo
- rfo, rfw
Answer :- a
28. Which rf edge involves read and write operations from the same thread?
- rfe
- rfi
- rfo
- rfw
Answer :- b
29. Write Serialization (ws) and from-read (fr) edges are, respectively:
- Global, global
- Local, local
- Local, global
- Global, local
Answer :- a
30. Consider the following statements.
S1: If every access graph is cyclic, then PLSC is upheld across all memory locations.
S2: An acyclic causal graph ensures the absence of thin air reads.
- Only S1 is true.
- Only S2 is true.
- Both S1 and S2 are true.
- Both S1 and S2 are false.
Answer :- c
31. Cache coherence protocols that use buses are known as ___________ protocols.
- Directory
- Snoopy
- Write-Through
- Write-Allocate
Answer :- b
32. Consider the following statements.
S1: Snoopy protocols are easy to design but hard to scale.
S2: All the messages are essentially broadcast messages in a snoopy protocol.
- Only S1 is true.
- Only S2 is true.
- Both S1 and S2 are true.
- Both S1 and S2 are false.
Answer :- c
33. Which of the following is not a type of message that the directory receives in a directory protocol?
- RdX
- WrX
- Evict
- Share
Answer :- d
34. Which of the following is false regarding the directory protocol?
- The directory itself can be a point of contention
- Directory protocol requires the broadcasting of all the messages.
- We need an entry for each block of a program’s working set.
- In each directory entry, we need an entry for each constituent cache.
Answer :- d
35. Consider the following statements.
S1: A distributed directory solves the issue of a single point of contention in the directory protocol.
S2: In uniprocessor systems, false sharing can cause inefficiency.
- Only S1 is true.
- Only S2 is true.
- Both S1 and S2 are true.
- Both S1 and S2 are false.
Answer :- c
36. A/an ______________ algorithm ensures no starvation.
- Altruistic
- Lock-free
- Test and set
- Compare and set
Answer :- a
37. PLSC requires the __________ and ___________ orders to be global.
- rf, po
- fr, po
- ws, fr
- ws, rf
Answer :- a
38. Two accesses are said to be concurrent when there is no path between them in the execution witness that contains a/an _________ edge.
- so
- po
- ws
- rf
Answer :- d
39. Consider the following statements.
S1: SC implies data-race freedom.
S2: PLSC implies data-race freedom.
- Only S1 is true.
- Only S2 is true.
- Both S1 and S2 are true.
- Both S1 and S2 are false.
Answer :- a
40. The consensus number is the _ number of threads that can solve the problem using a _________algorithm.
- Maximum, wait-free
- Minimum, wait-free
- Minimum, lock-free
- Maximum, lock-free
Answer :- b